// sdram_interface.v

// Generated using ACDS version 18.0 614

`timescale 1 ps / 1 ps
module sdram_interface (
		input  wire [23:0] avs_address,       //     avs.address
		input  wire [1:0]  avs_byteenable_n,  //        .byteenable_n
		input  wire        avs_chipselect,    //        .chipselect
		input  wire [15:0] avs_writedata,     //        .writedata
		input  wire        avs_read_n,        //        .read_n
		input  wire        avs_write_n,       //        .write_n
		output wire [15:0] avs_readdata,      //        .readdata
		output wire        avs_readdatavalid, //        .readdatavalid
		output wire        avs_waitrequest,   //        .waitrequest
		input  wire        clk_clk,           //     clk.clk
		output wire [12:0] mem_pin_addr,      // mem_pin.addr
		output wire [1:0]  mem_pin_ba,        //        .ba
		output wire        mem_pin_cas_n,     //        .cas_n
		output wire        mem_pin_cke,       //        .cke
		output wire        mem_pin_cs_n,      //        .cs_n
		inout  wire [15:0] mem_pin_dq,        //        .dq
		output wire [1:0]  mem_pin_dqm,       //        .dqm
		output wire        mem_pin_ras_n,     //        .ras_n
		output wire        mem_pin_we_n,      //        .we_n
		input  wire        reset_reset_n      //   reset.reset_n
	);

	wire    rst_controller_reset_out_reset; // rst_controller:reset_out -> sdram_controller:reset_n

	sdram_interface_sdram_controller sdram_controller (
		.clk            (clk_clk),                         //   clk.clk
		.reset_n        (~rst_controller_reset_out_reset), // reset.reset_n
		.az_addr        (avs_address),                     //    s1.address
		.az_be_n        (avs_byteenable_n),                //      .byteenable_n
		.az_cs          (avs_chipselect),                  //      .chipselect
		.az_data        (avs_writedata),                   //      .writedata
		.az_rd_n        (avs_read_n),                      //      .read_n
		.az_wr_n        (avs_write_n),                     //      .write_n
		.za_data        (avs_readdata),                    //      .readdata
		.za_valid       (avs_readdatavalid),               //      .readdatavalid
		.za_waitrequest (avs_waitrequest),                 //      .waitrequest
		.zs_addr        (mem_pin_addr),                    //  wire.export
		.zs_ba          (mem_pin_ba),                      //      .export
		.zs_cas_n       (mem_pin_cas_n),                   //      .export
		.zs_cke         (mem_pin_cke),                     //      .export
		.zs_cs_n        (mem_pin_cs_n),                    //      .export
		.zs_dq          (mem_pin_dq),                      //      .export
		.zs_dqm         (mem_pin_dqm),                     //      .export
		.zs_ras_n       (mem_pin_ras_n),                   //      .export
		.zs_we_n        (mem_pin_we_n)                     //      .export
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~reset_reset_n),                 // reset_in0.reset
		.clk            (clk_clk),                        //       clk.clk
		.reset_out      (rst_controller_reset_out_reset), // reset_out.reset
		.reset_req      (),                               // (terminated)
		.reset_req_in0  (1'b0),                           // (terminated)
		.reset_in1      (1'b0),                           // (terminated)
		.reset_req_in1  (1'b0),                           // (terminated)
		.reset_in2      (1'b0),                           // (terminated)
		.reset_req_in2  (1'b0),                           // (terminated)
		.reset_in3      (1'b0),                           // (terminated)
		.reset_req_in3  (1'b0),                           // (terminated)
		.reset_in4      (1'b0),                           // (terminated)
		.reset_req_in4  (1'b0),                           // (terminated)
		.reset_in5      (1'b0),                           // (terminated)
		.reset_req_in5  (1'b0),                           // (terminated)
		.reset_in6      (1'b0),                           // (terminated)
		.reset_req_in6  (1'b0),                           // (terminated)
		.reset_in7      (1'b0),                           // (terminated)
		.reset_req_in7  (1'b0),                           // (terminated)
		.reset_in8      (1'b0),                           // (terminated)
		.reset_req_in8  (1'b0),                           // (terminated)
		.reset_in9      (1'b0),                           // (terminated)
		.reset_req_in9  (1'b0),                           // (terminated)
		.reset_in10     (1'b0),                           // (terminated)
		.reset_req_in10 (1'b0),                           // (terminated)
		.reset_in11     (1'b0),                           // (terminated)
		.reset_req_in11 (1'b0),                           // (terminated)
		.reset_in12     (1'b0),                           // (terminated)
		.reset_req_in12 (1'b0),                           // (terminated)
		.reset_in13     (1'b0),                           // (terminated)
		.reset_req_in13 (1'b0),                           // (terminated)
		.reset_in14     (1'b0),                           // (terminated)
		.reset_req_in14 (1'b0),                           // (terminated)
		.reset_in15     (1'b0),                           // (terminated)
		.reset_req_in15 (1'b0)                            // (terminated)
	);

endmodule
